AIM-Spice circuit descriptions of the examples

AIM-Spice Example Circuit Files

Introduction to device Modeling and Circuit Simulation

John Wiley & Sons, New York (1998)

ISBN 0-471-15778-3

T. A. Fjeldly, T. Ytterdal, and M. S. Shur

Instruction: Copy the file (netlist) of choice into the text editor of the main AIM-Spice window and follow the instructions in Section A1.2 of Appendix A1 of the book. See also the tutorial in Section 1.3 of Chapter 1. For a discussion of each example, see the pages indicated.

Chapter 1

Simulation tutorial, BJT differential pair, pp.18-27

DIFFPAIR CKT - SIMPLE DIFFERENTIAL PAIR

VIN 1 0 DC 0 PULSE(-0.5 0.5 0.1u 1n 1n 0.3u 2u) AC 1

VCC 8 0 12

VEE 9 0 -12

Q1 4 2 6 QNL

Q2 5 3 6 QNL

RS1 1 2 1K

RS2 3 0 1K

RC1 4 8 10K

RC2 5 8 10K

Q3 6 7 9 QNL

Q4 7 7 9 QNL

RBIAS 7 8 20K

.MODEL QNL NPN(BF=80 RB=100 CJS=2PF TF=0.3NS TR=6NS

+ CJE=3PF CJC=2PF VA=50)

Chapter 3

Simple voltage regulator, pp.67-69

Simple Voltage Regulator

Vp 1 0 dc 10

Vf 1 2 dc 0 sin(0 1 50)

r1 2 3 1k

d1 3 4 diode

d2 4 5 diode

d3 5 6 diode

d4 6 0 diode

.model diode d is=880.5E-18 rs=.25 ikf=0 n=1

+ xti=3 eg=1.11 cjo=175p m=0.5516 vj=.75 fc=.5

+ isr=1.859n nr=2 bv=4.7 ibv=20.245m

Temperature dependence of diode characteristics, pp.69-72

Temperature dependence of diode current

vd 1 0 dc 0

vid 1 2 dc 0

d1 2 0 dmod temp=27

* Motorola 1N750

.model dmod d Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3

+ Eg=1.11 Cjo=175p M=.5516 Vj=.75 Fc=.5 Isr=1.859n

+ Nr=2 Bv=4.7 Ibv=20.245m

Heterostructure diode characteristics, pp.79-80

HDIA I-V curve

vin 1 0 dc 0

vid 1 2 dc 0

d1 2 0 diode

.MODEL diode d level=2 dn=0.02 dp=0.000942 ln=7.21e-5

+ lp=8.681e-7 nd=7e24 na=3e22 deltaec=9.613150e-20

+ xp=1e-6 xn=1e-6 epsp=1.0593e-10 epsn=1.1594e-10

+ rs=20

Diode switching transients, pp.88-91

Switching diode

vd 1 0 dc 0 pwl (0,1 5n,1 5.01n,0 50n,0)

vid 1 2 dc 0

d1 2 0 dmod

.model dmod d IS=0.1p RS=16 CJO=2p TT=12n

Chapter 4

Emitter-coupled logic, Ebers-Moll model, pp.124-125

ECL OR gate with NOR output

Ve1 1 0 dc -5.2

Ve2 13 0 dc -2.0

Va 12 0 dc 0 pwl(0,-1.77V 2ns,-1.77V 3ns,

+ -0.884V 30ns,-0.884V)

Vb 11 0 dc -1.77

Qa 2 12 10 npnmod

Qb 2 11 10 npnmod

Qr 3 5 10 npnmod

Q2 0 3 9 npnmod

Q3 0 2 8 npnmod

Ra 12 1 50k

Rb 11 1 50k

Re 10 1 779

Rc1 0 2 220

Rc2 0 3 245

Rt2 9 13 50

Rt3 8 13 50

Vr 5 0 -1.32V

.model npnmod npn IS=0.30fA BF=120 BR=1

+ TF=0.15ns CJE=1.5pF CJC=1.5pF

Common-emitter current gain, pp.132-133

Circuit for calculating the common-emitter current gain

vb 1 0 dc 0

vib 1 2

vic 4 3

vce 4 0 dc 4

q1 3 2 0 qn

.model qn npn Is=14.34f Xti=3 Eg=1.11 Bf=100 Ne=2

+ Ise=143.4f Xtb=1.5 Br=9.715 Nc=2 Isc=0 Rc=1

+ Itf=.6 Vtf=1.7 Xtf=3

Small-signal frequency response, pp.137-139

Simple common-emitter voltage amplifier (Ib = 1 uA)

vc 1 0 dc 2

vic 1 2 dc 0

ib 0 3 dc 0.001m ac 1

q1 2 3 0 npnmod

.model npnmod npn Is=14.34f Xti=3 Eg=1.11 Vaf=74.03

+ Bf=65.62 Ne=1.208 Ise=19.48f Ikf=.2385 Xtb=1.5

+ Br=9.715 Nc=2 Isc=0 Ikr=0 Rc=0 Cjc=9.393p Mjc=.3416

+ Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=58.98n

+ Tf=408.8p Itf=.6 Vtf=1.7 Xtf=3 Rb=10

Chapter 5

MOSFET I-V characteristics, pp.183-185

MOSFET I-V characteristics

vds 1 0 dc 0

vids 1 100 dc 0

m1 100 2 0 0 mn l=0.6u w=50u

vgs 2 0 dc 0

.model mn nmos level=1 vto=0.51 tox=100E-10

+ u0=610 ld=0.07u rs=20 rd=20

MOSFET level 3 model:

.model mn nmos level=3 vmax=1e5 vto=0.51 tox=100E-10

+ u0=610 ld=0.07u rs=20 rd=20 theta=0.03 delta=0

+ eta=0.01 nfs=1.3e12

MESFET subthreshold characteristics, pp.193-195

Mesfet subthreshold characteristics

Vds 1 0

vids 1 2 dc 0

Vgs 3 0 dc 0

z1 2 3 0 mesmod a=1.4

.model mesmod nmf level=1 rd=46 rs=46 vt0=-1.3

+ lambda=0.03 alpha=3 beta=1.4e-3

* z1 2 3 0 lev2 l=1u w=20u

* .model lev2 nmf level=2 d=0.12u mu=0.23 vs=1.8e5

*+ m=3.3 vto=-1.3 eta=1.82 lambda=0.044 sigma0=0.09

*+ vsigma=0.1 vsigmat=0.9 rdi=46 rsi=46 delta=5

*+ nd=2.1e23

HFET saturation characteristics, pp.196-197

HFET Id versus Vgs characteristic

m1 3 2 0 0 nlev3 l=1u w=10u

vgs 2 0 dc 0

vds 1 0 dc 0.1

vids 1 3 dc 0

.model nlev3 nmos level=3 vto=0.13 rd=0 rs=0

+ tox=250E-10 ld=0 vmax=1.5e5 kp=1e-3 theta=0

+ delta=1.5 eta=0.1 kappa=1

Using the universal HFET model, replace line 2 by

a1 3 2 0 hfet l=1u w=10u

and the model statement by

.model hfet nhfet rdi=0 rsi=0 m=2.57 lambda=0.17

+ vs=1.5e5 mu=0.385 vt0=0.13 eta=1.32 sigma0=0.04

+ vsigma=0.1 Vsigmat=0.3 js1s=0 js1d=0 nmax=6e15

HFET DCLF inverter, pp.199-201

DCFL inverter circuit

.subckt inv 1 2 3

*Vdd 1.0

*Vin 2 0

*Vout 3 0

a1 1 3 3 aload l=1u w=10u

a2 3 2 0 adrv l=1u w=10u

.ends

vdd 1 0 dc 2

vin 2 0 dc 0 pwl(0,0V 1ns,0V 1.005ns,1V 2ns,1V)

x1 1 2 3 inv

x2 1 3 4 inv

.model adrv nhfet rd=60 rs=60 m=2.57 lambda=0.17

+ vs=1.5e5 mu=0.385 vt0=0.3 eta=1.32 sigma0=0.04

+ vsigma=0.1 vsigmat=0.3 js1s=1e-12 js1d=1e-12

+ nmax=6e15

.model aload nhfet rd=60 rs=60 m=2.57 lambda=0.17

+ vs=1.5e5 mu=0.385 vt0=-0.3 eta=1.32 sigma0=0.04

+ vsigma=0.1 vsigmat=0.3 js1s=1e-12 js1d=1e-12

+ nmax=6e15

Chapter 6

CMOS operational amplifier, pp.231-233

A Simple CMOS OPAMP

* Power supply and bias current source

vdd 9 0 dc 2.5

vss 6 0 dc -2.5

ibias 7 0 dc 5.19ua

* Amplifier

m1 4 1 3 3 mp l=2u w=18u

m2 5 2 3 3 mp l=2u w=18u

m3 4 5 6 6 mn l=2u w=3u

m4 5 5 6 6 mn l=2u w=3u

m5 8 7 9 9 mp l=2u w=6u

m6 8 4 6 6 mn l=2u w=18u

m7 3 7 9 9 mp l=2u w=2u

m8 7 7 9 9 mp l=2u w=2u

rc 10 8 7042

cc 4 10 200fF

* Input biasing circuit (not shown in figure)

vin 101 0 dc 0 ac 1 pwl(0,0V 100ns,0V 103ns,100mV 200ns,100mV)

rd 101 0 1

ev+ 1 0 101 0 +0.5

ev- 2 0 101 0 -0.5

.model mn nmos level=7 vto=0.736 gammas0=0.825 phi=0.686 pb=0.8

+js=3.2e-5 tox=250e-10 nsub=8e15 xj=0.25e-6 ld=0.24e-6 vmax=5e4

+ uo=418 eta=1.745 lambda=0.00969 m=2.9 sigma0=0.0065

+ cgdo=1.27E-10 cgso=1.27E-10 cgbo=7.66E-11 cj=570E-6 mj=0.3

+ cjsw=260E-12 mjsw=0.33 rs=12.87 rd=12.87

.model mp pmos level=7 vto=-0.622 gammas0=0.514 phi=0.635

+ pb=0.635 js=3.2e-5 tox=250e-10 nsub=3e15 xj=0.4e-6 ld=0.3e-6

+ vmax=2.5e4 uo=195 eta=1.745 lambda=0.0429 m=3 sigma0=0.0065

+ cgdo=1.27E-10 cgso=1.27E-10 cgbo=7.66E-11 cj=190E-6 mj=0.3

+ cjsw=260E-12 mjsw=0.33 rs=76.45 rd=76.45

MESFET ring oscillator, pp.244-247

Mesfet Ring Oscillator with ungated load

.subckt mesinv 10 20 30

* Node 10: Power Supply

* Node 20: Input

* Node 30: Output

rdl 10 1 20

bl 1 2 i=0.00025*tanh(v(1,2)/0.00025/2240)*

+(1+v(1,2)*0.027)

rsl 2 30 20

zd 30 20 0 driver l=0.7u w=20u

ci 30 0 20f

.ends mesinv

.model driver nmf level=2 n=1.44 rd=20 rs=20 vs=1.9e5

+ mu=0.25 d=1e-7 vto=0.15 m=2 lambda=0.15 sigma0=0.02

+ vsigmat=0.5

vdd 1 0 dc 1.6

xinv01 1 2 3 mesinv

xinv02 1 3 4 mesinv

xinv03 1 4 5 mesinv

xinv04 1 5 6 mesinv

xinv05 1 6 7 mesinv

xinv06 1 7 8 mesinv

xinv07 1 8 9 mesinv

xinv08 1 9 10 mesinv

xinv09 1 10 11 mesinv

xinv10 1 11 12 mesinv

xinv11 1 12 2000 mesinv

vnoise 2000 2 dc 0 pwl(0 0 0.2n 0 0.3n 0.1 0.4n 0)

HFET gate leakage current, pp.253-255

Circuit for calculating gate leakage current

a1 4 2 5 hfet l=1u w=10u

vgs 3 0 dc 0

vds 1 0 dc 0.2

vig 3 2 dc 0

vid 1 4 dc 0

vis 5 0 dc 0

.model hfet nhfet rd=60 rs=60 js1d=0 js1s=0

HFET DCFL inverter, pp.256-257

Circuit for calculating gate leakage current

a1 4 2 5 hfet l=1u w=10u

vgs 3 0 dc 0

vds 1 0 dc 0.2

vig 3 2 dc 0

vid 1 4 dc 0

vis 5 0 dc 0

.model hfet nhfet rd=60 rs=60 js1d=0 js1s=0

a-Si TFT EEL inverter inverter, pp.263-264

a-Si TFT EEL Inverter

m1 1 1 2 0 TFTL l=8u w=80u

m2 2 3 0 0 TFTD l=8u w=80u

vin 3 0 dc 0

vdd 1 0 dc 10

.model TFTL nmos level=15 vto=2.5 tox=0.1u

.model TFTD nmos level=15 vto=5 tox=0.1u

Poly-Si TFT inverter, pp.266-267

Poly-Si Inverter with depletion load

m1 1 2 2 0 TFTL l=30u w=50u

m2 2 3 0 0 TFTD l=30u w=50u

vin 3 0 dc 0

vds 1 0 dc 30

.model TFTL nmos level=12 vto=-10 uo=85.0 tox=1000e-10

.model TFTD nmos level=12 vto=2.5 uo=85.0 tox=1000e-10