1.1. Introduction / 1

1.2. SPICE and Beyond / 7

1.2.1. Historical Overview and Versions of SPICE / 7

1.2.2. Principle of Operation / 8

1.2.3. Beyond SPICE / 12

1.3. SPICE Simulation Tutorial / 18

References / 27

Problems / 28

2.1. Introduction / 30

2.2. Basic Semiconductor Equations / 30

2.3. Material Properties of Important Semiconductors / 36

References / 41

Problems / 41

3.1. Introduction / 43

3.2. p-n Junctions / 45

3.2.1. p-n Junctions at Equilibrium / 45

3.2.2. Current-Voltage Characteristic of an Ideal p-n Diode / 50

3.2.3. Non-Ideal Effects / 55

3.2.4. Capacitance and Small-Signal Equivalent Circuit / 61

3.2.5. SPICE Implementation of p-n Diode Model / 65

3.2.6. SPICE Example: Simple Voltage Regulator / 67

3.2.7. SPICE Example: Temperature Dependence of Diode

Characteristics / 69

3.2.8. SPICE Example: Temperature Dependence of Voltage Regulator / 72

3.2.9. SPICE Example: Capacitance-Voltage Characteristics of Diode / 72

3.3. Heterojunctions / 74

3.3.1. Basic Concepts / 74

3.3.2. Current-Voltage Characteristic / 77

3.3.3. Heterojunction Capacitance / 78

3.3.4. SPICE Implementation of Heterostructure Diode Model / 79

3.3.5. SPICE Example: Heterostructure Diode Characteristics / 79

3.4. Metal-Semiconductor Junctions / 81

3.4.1. Schottky Barriers / 81

3.4.2. Schottky Barrier Current-Voltage Characteristic / 85

3.4.3. Schottky Barrier Capacitance / 86

3.4.4. Ohmic Contacts / 87

3.4.5. SPICE Example: Diode Switching Transients / 88

3.5. The Metal Insulator Semiconductor Capacitor / 91

3.5.1. Interface Charge / 91

3.5.2. Threshold Voltage / 97

3.5.3. MIS Capacitance / 98

3.5.4. Unified Charge Control Model for MIS Capacitors / 102

References / 104

Problems / 104

4.1. Introduction / 109

4.2. BJT Basics / 110

4.2.1. Modes of Operation / 111

4.2.2. Current-Voltage Characteristics of BJTs / 11536Mon ofEation of istic of BJTs

4.3. BJT Modeling / 120

4.3.1. Ebers-Moll Model / 120

4.3.2. SPICE Example: Emitter Coupled Logic / 124

4.3.3. Gummel-Poon Model / 125

4.3.4. Implementation of Gummel-Poon Model in SPICE / 130

4.3.5. SPICE Example: Common-Emitter Current Gain / 132

4.3.6. BJT Small-Signal Modeling / 133

4.3.7. SPICE Example: Small-Signal Frequency Response / 137

4.4. Heterojunction Bipolar Transistor / 139

4.4.1. Principle of Operation / 139

4.4.2. Thermionic-Emission-Diffusion Model for HBT / 142

4.4.3. Non-Ideal Effects in the HBT Model / 144

4.4.4. Implementation of HBT Model in AIM-Spice / 146

References / 148

Problems / 148

5.1. Introduction / 154

5.2. Principles of Operation / 157

5.2.1. MOSFET Operation / 157

5.2.2. MESFET Operation / 160

5.2.3. HFET Operation / 161

5.2.4. Amorphous Silicon TFT Operation / 163

5.2.5. Polysilicon TFT Operation / 164

5.3. Basic MOSFET Models / 166

5.3.1. Gradual Channel Approximation / 166

5.3.2. The Meyer I–V Model / 167

5.3.3. Simple Charge Control Model / 170

5.3.4. Velocity Saturation Model / 175

5.3.5. Comparison of Basic MOSFET Models / 178

5.3.6. SPICE Implementation of Basic MOSFET Models / 180

5.3.7. SPICE Example: MOSFET I–V Characteristics / 183

5.4. Basic MESFET Models / 185

5.4.1. The Shockley Model / 185

5.4.2. Velocity Saturation Models / 190

5.4.3. SPICE Implementation of Basic MESFET Model / 193

5.4.4. SPICE Example: MESFET Subthreshold Characteristics / 193

5.5. Basic HFET Model / 195

5.5.1. SPICE Example: HFET Saturation Characteristics / 196

References / 201

Problems / 201

6.1. Introduction / 206

6.1.1. Challenges in Advanced FET Modeling / 207

6.1.2. Advanced FET Modeling Approach / 208

6.2. Universal FET Modeling Approach / 210

6.2.1. Unified Charge Control Model for FETs / 210

6.2.2. Basics of the Universal FET Model / 212

6.2.3. High-Field Effects / 218

6.2.4. Short-Channel Effects / 222

6.3. Universal MOSFET Model / 224

6.3.1. MOSFET I–V Model / 224

6.3.2. MOSFET C–V Model / 226

6.3.3. Implementation in AIM-Spice / 228

6.3.4. SPICE Example: CMOS Operational Amplifier / 231

6.4. Universal MESFET Model / 232

6.4.1. MESFET I–V Model / 234

6.4.2. MESFET C–V Model / 237

6.4.3. Implementation in AIM-Spice / 242

6.4.4. SPICE Example: MESFET Ring Oscillator / 244

6.5. Universal HFET Model / 246

6.5.1. HFET I–V Model / 248

6.5.2. HFET C–V Model / 250

6.5.3. Implementation in AIM-Spice / 253

6.5.4. SPICE Example: Gate Leakage in HFETs / 253

6.6. Universal a-Si:H TFT Model / 257

6.6.1. a-Si:H TFT I–V Model / 260

6.6.2. a-Si:H TFT C–V Model / 261

6.6.3. SPICE Example: a-Si:H TFT EEL inverter / 263

6.7. Universal Poly-Si TFT Model / 264

6.7.1. Poly-Si TFT I–V Model / 265

6.7.2. Poly-Si TFT C–V Model / 266

6.7.3. SPICE Example: Poly-Si TFT Inverter / 266

6.8. BSIM3 MOSFET Model / 268

6.8.1. Threshold Voltage / 268

6.8.2. Effective Carrier Mobility / 270

6.8.3. Unified Drain Current / 270

6.8.4. Intrinsic Capacitance Model / 271

6.8.5. Non-Quasi-Static Model / 271

References / 274

Problems / 276

A1. AIM-Spice Users Manual / 282

A1.1. Introduction / 282

A1.2. AIM-Spice / 283

A1.3. AIM-Postprocessor / 308

References / 330

A2. AIM-Spice Reference / 331

A2.1. Introduction / 331

A2.2. Types of Analyses / 332

A2.3. Model Parameter Specifications / 337

References / 394

A3. Temperature Dependence of Mobilities in Silicon / 395

References / 396

A4. Parasitic Series Resistances in FETs / 397

References / 399